System and method for generating a cyclic redundancy check

ABSTRACT

A Cyclic Redundancy Check (CRC) system comprises N+1 shift registers. N+1 logic gates having first inputs communicate with outputs of corresponding ones of said N+1 shift registers. N+1 programmable registers store a corresponding CRC coefficient of a 3 rd  to Nth order CRC polynomial key word, wherein N is an integer greater than two. N+1 multiplexers communicate with outputs of corresponding ones of said N+1 logic gates. At least N of said N+1 multiplexers communicate with corresponding ones of at least N of said N+1 programmable registers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. Ser. No. 10/039,585 filed onJan. 4, 2002, which application claims the priority benefit of U.S.Provisional Patent Application Ser. No. 60/338,137, filed Nov. 9, 2001,entitled, “SYSTEM AND METHOD FOR GENERATING A CYCLIC REDUNDANCY CHECK”.All of these applications are hereby incorporated by reference in theirentirety.

FIELD OF THE INVENTION

The invention generally relates to electronic systems. The inventionrelates more specifically to systems and methods for generating cyclicredundancy check.

BACKGROUND OF THE INVENTION

A popular method for error detection for digital signals is the CyclicRedundancy Check (CRC). CRC works by treating the message string that issent between a transmitter and a receiver as a single binary word. Thesingle binary word is divided by a key word that is agreed upon by boththe transmitter and the receiver ahead of time. The remainder that isleft after dividing the single binary word by the key word is known as acheck word. The transmitter sends both the message string and the checkword to the receiver. The receiver then verifies the data by dividingthe data by the key word. If the remainder, obtained by dividing thedata by the key word, matches the check word, then the receiver can besure that the data is indeed the correct message string from thetransmitter.

In the context of CRC, key words are usually numbers and are presentedin the form of polynomials whose coefficients are in the form of thebinary bits of the key word. A popular key word is X¹⁶+X¹²+X⁵+1 known asthe X25 standard. Key words will herein be referred to as polynomial keywords.

CRC is often implemented in hardware that is specific to a givenpolynomial key word. A CRC that is implemented in hardware is hereinreferred to as a CRC generator. Thus, a system that has to verify datausing various different polynomial key words will need a separate CRCgenerator that is dedicated to each distinct polynomial key word. Forexample, FIG. 1 is a block diagram that illustrates a CRC generator thatemploys a 3^(rd) order polynomial key word, X³+X²+1.

In FIG. 1, exclusive-OR gates (XOR gates) 110, 112, and 116 arecommunicatively coupled to each other and to corresponding shiftregisters 102, 104 and 106. Input 101 is initially received at XOR gate110. The output of the CRC generator in FIG. 1 is 118.

FIG. 2 is block diagram that illustrates a CRC generator that employs a1st order polynomial key word, X¹+1. In FIG. 2, XOR gates 210, and 212are communicatively coupled to each other and to corresponding shiftregisters 202, and 204. Input 220 is initially received at XOR gate 210.The output of the CRC generator in FIG. 2 is 222. A system with multipleCRC generators can be unwieldy and inefficient.

SUMMARY OF THE INVENTON

A Cyclic Redundancy Check (CRC) system comprises N+1 shift registers.N+1 logic gates having first inputs communicate with outputs ofcorresponding ones of said N+1 shift registers. N+1 programmableregisters store a corresponding CRC coefficient of a 3^(rd) to Nth orderCRC polynomial key word, wherein N is an integer greater than two. N+1multiplexers communicate with outputs of corresponding ones of said N+1logic gates. At least N of said N+1 multiplexers communicate withcorresponding ones of at least N of said N+1 programmable registers.

Further areas of applicability will become apparent from the descriptionprovided herein. It should be understood that the description andspecific examples are intended for purposes of illustration only and arenot intended to limit the scope of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by wayof limitation, in the figures of the accompanying drawings and in whichlike reference numerals refer to similar elements and in which:

FIG. 1 is a block diagram that illustrates a prior art CRC generatorthat employs a 3^(rd) order polynomial key word;

FIG. 2 is block diagram that illustrates a prior art CRC generator thatemploys a 1st order polynomial key word;

FIG. 3A is block diagram that illustrates an exemplary N-bit capable CRCgenerator;

FIG. 3B is a block diagram that illustrates the most significant bit(MSB) to the least significant bit (LSB) in relation to programmableregisters;

FIG. 4 is a block diagram that illustrates the position of the MSB thatis associated with a q^(th) order polynomial key word;

FIG. 5 is a block diagram that illustrates a 3-bit capable CRCgenerator;

FIG. 6 is a block diagram that illustrates the position of the MSB thatis associated with a X³+X²+1 key word;

FIG. 7 is a block diagram that illustrates the position of the MSB thatis associated with a X¹+X⁰ key word;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A system and method for generating a cyclic redundancy check isdescribed. In the following description, for the purposes ofexplanation, numerous specific details are set forth in order to providea thorough understanding of the present invention. It will be apparent,however, to one skilled in the art that the present invention may bepracticed without these specific details. In other instances, well-knownstructures and devices are shown in block diagram form in order to avoidunnecessarily obscuring the present invention. Embodiments are describedherein according to the following outline:

1.0 OPERATIONAL CONTEXT AND FUNCTIONAL OVERVIEW

2.0 N-BIT CAPABLE CRC GENERATOR

3.0 ILLUSTRATIVE EXAMPLE OF THE FLEXIBILITY OF AN N-BIT CAPABLE CRCGENERATOR

5.0 EXTENSIONS AND ALTERNATIVES

1.0 Operational Context and Functional Overview

In certain embodiments of the present invention, a universal CRCgenerator is used in a system that receives digital signals. Theuniversal CRC generator can be programmed to be a specific polynomialkey word CRC generator. Thus, one set of hardware can be adapted for anygiven polynomial key word. For example, for purposes of explanation,assume that a transmitter of a bitstream and a receiver of the samebitstream agree upon a key word that can be represented by thepolynomial, X¹⁶+X¹²+X⁵+1. The universal CRC can be programmed to be anX¹⁶+X¹²+X⁵+1 polynomial key word CRC generator. Generally, an N^(th)polynomial key word CRC generator is also referred to as an N-bit CRCgenerator. Each time that the key word is changed, the universalCRC_(generator) can be re-programmed to correspond to the new key word.It is to be noted that an N^(th) order polynomial key word has (N+1)bits.

Thus, in certain embodiments of the present invention, the universal CRCgenerator is a CRC generator that is capable of being a N-bit CRCgenerator, where N is a positive integer that is selected correspondingto the highest order polynomial key word that the universal CRCgenerator is expected to use. A universal generator that is capable ofbeing an N-bit CRC generator is herein referred to as an “N-bit capable”CRC generator.

According to certain embodiments of the present invention, the universalCRC generator can be re-programmed to correspond to a new polynomial keyword by programming the values of certain programmable registers thatare part of the universal CRC generator and by programming certainselection inputs for multiplexers that are also part of the universalCRC generator. The programming of the registers and selection inputs forthe multiplexers are explained in greater detail herein.

2.0 N-Bit Capable CRC Generator

According to certain embodiments of invention, FIG. 3A is block diagramthat illustrates an N-bit capable CRC generator. An N-bit capable CRCgenerator is a universal CRC generator for which the highest orderpolynomial key word is N. Thus, an N-bit capable CRC generator can beused for polynomial key words of orders ranging from 1 to N. The N-bitCRC generator of FIG. 3A comprises the following as indicated in List A.

List A:

1) N+1 number of shift registers, namely, X^(n) 310, X^((n−1)) 312, . .. , X⁰ 314;

2) N+1 number of exclusive-OR gates, namely, XOR^(n) 316, XOR^((n−1))318, . . . , XOR⁰ 320;

3) 3N+1 number of multiplexers, namely, M_(a) ^(n) 322, M_(a) ^((n−1))324, M_(b) ^((n−1)) 326, M_(c) ^((n−1)) 328, . . . , M_(a) ⁰ 330, M_(b)⁰ 332, M_(c) ⁰ 334; and

4) N+1 programmable registers, namely, Y^(n) 336, Y^((n−1)) 338, . . . ,Y⁰ 340.

The broken line 302 in FIG. 3A indicates that the following componentsas indicated in List B are not shown on FIG. 3A for want of space.

List B:

1) shift registers X^((n−2)), X^((n−3)), up to X¹;

2) exclusive-OR gates XOR^((n−2)), XOR^((n−31)), . . . , up to XOR¹;

3) multiplexes M_(a) ^((n−2)), M_(b) ^((n−2)), M_(c) ^((n−2)), . . . ,up to M_(a) ¹, M_(b) ¹, M_(c) ¹;

4) programmable registers Y^((n−2)), Y^((n−3)), . . . , up to Y¹;

Each of the shift registers X is communicatively coupled to acorresponding exclusive-OR gate (XOR gate) and to adjacent multiplexersM. For example, in FIG. 3A, shift register X^(n) 310 is communicativelycoupled to a corresponding XOR gate, XOR^(n) 316. Specifically, line 368is shown as the output from X^(n) 310. Line 368 is also the input to XORgate, XOR^(n) 316. Similarly, shift register X^(n−1) 312 iscommunicatively coupled to a corresponding XOR gate, XOR^(n−1) 318, etc.Line 378 is shown as the output from X^(n−1) 312. Line 378 is also theinput to XOR gate, XOR^(n−1) 318. However, shift register X⁰ 314 iscommunicatively coupled to only one XOR gate, viz., XOR⁰ 320. Line 390is shown as the output from X⁰ 314. Line 390 is also the input to XORgate, XOR⁰ 320.

Further, each of the shift registers X in FIG. 3A is communicativelycoupled to corresponding adjacent multiplexers M. For example, shiftregister X^(n) 310 is communicatively coupled to adjacent multiplexersM_(a) ^(n) 322 and M^(a(n−1)) 324. Specifically, line 366 is shown as anoutput from shift register X^(n) 310. Line 366 is also the input tomultiplexer M_(a) ^(n) 322. Line 372 is shown as an output frommultiplexer M_(a) ^(n−1) 324. Line 372 is also an input to shiftregister X^(n) 310.

Similarly, shift register X^(n−1) 312 is communicatively coupled toadjacent multiplexers M_(a) ^(n−1) 324, etc. Specifically, line 376 isshown as an output from shift register X^(n−1) 312. Line 376 is also theinput to multiplexer M_(a) ^(n−1) 324. Line 382 is shown as an outputfrom multiplexer M_(a) ^(n−2) (note that M_(a) ^(n−2) is not shown inFIG. 3A). Line 382 is also an input to shift register X^(n−1) 312.

Shift register X⁰ 314 is communicatively coupled to adjacent multiplexerM_(a) ⁰ 330. Specifically, line 391 is shown as an output line fromshift register X⁰ 314. Line 391 is also an input line to multiplexerM_(a) ⁰ 330. Line 393 is shown as an output line from multiplexer M_(b)⁰ 332. Line 393 is also an input line to shift register X⁰ 314

Further, all shift registers X^(n) 310, X^((n−1)) 312, . . . , X⁰ 314 inFIG. 3A are communicatively coupled to multiplexer M_(out) 342 via linesAn 344, A^(n−1) 346, . . . , up to A⁰ 348. For example, shift registerX^(n) 310 is connected to M_(out) 342 via line A^(n) 344. Shift registerX^(n−1) 312 is connected to M_(out) 342 via line A^(n−1) 346, etc.Further, CRC output 350 is the output of the N-bit capable CRCgenerator.

Each XOR gate is additionally communicatively coupled to correspondingadjacent multiplexers. For example, in FIG. 3A, XOR gate XOR^((n−1)) 318is communicatively coupled to adjacent corresponding multiplexersM^(a(n−1)) 324 and M_(c) ^((n−1)) 328. Specifically, line 380 is shownas an input line from multiplexer M_(c) ^((n1−1)) 328 to XOR gateXOR^((n−1)) 318. Line 374 is an output line from XOR gate XOR^((n−1))318 to multiplexer M_(a) ^((n−1)) 324.

Similarly, XOR gate XOR⁰ 320, is communicatively coupled to adjacentcorresponding multiplexers M_(a) ⁰ 330 and M M_(c) ⁰ 334, etc.Specifically, line 396 is shown as an input line from multiplexer MM_(c) ⁰ 334 to XOR gate XOR⁰ 320. Line 388 is an output line from XORgate XOR⁰ 320 to multiplexer M_(a) ⁰ 330. However, XOR gate XOR^(n) 316is communicatively coupled to only one adjacent correspondingmultiplexer M_(a) ^(n) 322. Line 364 is shown as an output line fromXOR^(n) 316 to multiplexer M_(a) ^(n) 322.

Programmable registers Y^(n) 336, Y^((n−1)) 338, . . . , Y⁰ 340 are eachcommunicatively coupled to a corresponding multiplexer. For example,programmable register Y^(n) 336 is communicatively coupled tomultiplexer M_(a) ^(n) 322, programmable register Y^((n−1)) 338 iscoupled to multiplexer M_(a) ^((n−1)) 324, etc.

For simplicity, programmable registers Y^(n) 336, Y^((n−1)) 338, . . . ,Y⁰ 340 are collectively referred to herein as Y registers.

The Y registers are programmed based on the given polynomial key word.To explain, each Y register in the N-bit capable CRC generator isassociated with one term in the general Nth-order polynomial,C_(n)X^(n)+C_(n−1)X^(n−1)+C_(n−2)X^(n−2)+ . . . +C₂X²+C₁X¹+C₀X⁰, whereC_(n), C_(n−1), C_(n−2), . . . . , C₂, C₁, and C₀ are the coefficientsof the general N^(th)-order polynomial and are constants.

Each Y register corresponds to one coefficient of the generalN^(th)-order polynomial. Specifically, programmable register Y^(n) 336in FIG. 3A corresponds to coefficient C_(n), programmable registerY^(n−1) 338 corresponds to coefficient C_(n−1) and so on. The givenpolynomial key word is compared to the general N^(th) order polynomialto determine which of the coefficients of the general N^(th)-orderpolynomial are to take the value of zero in order to convert theN^(th)-order general polynomial into the given polynomial key word.

The Y registers that correspond to coefficients that have a value ofzero are programmed to have a bit value of zero. The Y registers thatcorrespond to coefficients that have a value of 1 are programmed to havea bit value of 1.

The value of each bit in the Y register determines which input isselected at the corresponding multiplexer to be an output. For example,if programmable register Y^(n) 336 is programmed to have a bit value of1, multiplexer M_(a) ^(n) 322 will receive the value 1 as an input fromprogrammable register Y^(n) 336. In FIG. 3A, it can be seen thatmultiplexer M_(a) ^(n) 322 has 2 input lines, labeled “1” and “0”respectively. Since the value 1 is received from programmable registerY^(n) 336 multiplexer M_(a) ^(n) 322 will select the input line labeled“1” to be the output of M_(a) ^(n) 322 for a particular cycle.

FIG. 3B is a block diagram that illustrates the most significant bit(MSB) to the least significant bit (LSB) in relation to the programmableregisters Y 370. Bit B_(n) corresponds to the value in register Y^(n)336, and is the MSB if the value of Y^(n) 336 is the first occurring “1”bit. Similarly, bit B_(n−1) corresponds to the value in register Y^(n−1)338, etc. Bit Bo corresponds to the value in register Y⁰ 340, and is theLSB.

For ease of explanation, multiplexers with the same superscript asillustrated in FIG. 3A are said to belong to the same family. As can beseen in FIG. 3A, multiplexers that belong to the same family arecommunicatively coupled to form part of a feedback loop. For example,multiplexer M_(a) ^((n−1)) 324 is communicatively coupled to multiplxerM_(b) ^((n−1)) 326 that is in turn communicatively coupled tomultiplexer M_(c) ^((n−1)) 328. Multiplexer M_(a) ⁰ 330 iscommunicatively coupled to multiplxer M_(b) ⁰ 332 that is in turncommunicatively coupled to multiplexer M_(c) ⁰ 334. However, multiplexerM_(a) ^(n) 322, being the sole member in its family is communicativelycoupled only to one multiplexer that belongs to another family, viz.,multiplexer M_(b) ^((n−1)) 326.

Selection inputs such as, Last-X^((n−1)) 352, Last-X^((n−2)) (not shownin FIG. 3A), . . . , Last-X⁰ 354, are received as inputs intocorresponding multiplexers with subscripts “b” and “c” and that belongto the same family. For example, Last-X^((n−1)) 352 is a selection inputinto multiplexers M_(b) ^((n−1)) 326 and M_(c) ^((n−1)) 328, and Last-X⁰354 is a selection input into multiplexers M_(b) ⁰ 332 and M_(c) ⁰ 334,etc.

Further, all selection inputs, namely, Last-X^((n−1)) 352,Last-X^((n−2)) (not shown in FIG. 3A), . . . , Last-X⁰ 354 are inputinto multiplexer M_(out) 342. It is to be noted that, in certainembodiments, there is no Last-X^(n) selection input.

For simplicity in explaining the function of the components in FIG. 3A,selection inputs such as Last-X^((n−1)) 352, Last-X^((n−2)) (not shownin FIG. 3A), . . . , Last-X⁰ 354 are collectively referred to herein asLast-X selection inputs.

Generally, selection inputs such as, Last-X^((n−1)) 352, Last-XX^((n−2)) (not shown in FIG. 3A), . . . , Last-X⁰ 354, are programmed tobe a specific value based on the most significant bit (MSB) of the Yregisters. For purposes of illustration, assume that the givenpolynomial key word is a q^(th) order polynomial, where q is a positiveinteger that is less than N. FIG. 4 is a block diagram that illustratesthe position of the MSB that is associated with a q^(th) orderpolynomial key word

In FIG. 4, bit B_(n) has the value of the Y^(n) register that isprogrammed as described herein. Bit B_(n−1) has the value of the Y^(n−1)register, bit B_(n−2) has the value of the Y^(n−2) register, . . . , bitB_(q) has the value of the Y^(q) register, bit B_(q-1), has the value ofthe Y_(q-1) register, bit B_(q-2) has the value of the Y^(q-2) register,. . . , bit B₂ has the value of the Y² register, bit B₁ has the value ofthe Y¹ register, and bit B₀ has the value of the Y⁰ register.

Since the given polynomial key word is a q^(th) order polynomial, thefirst occurring “1” bit corresponds to the value of the Y^(q) register.In FIG. 4, the first occurring “1” bit is in Y^(q) register and so Y^(q)is the MSB. Since the first “1” bit corresponds to the value of theY^(q) register, the i) selection input Last-X^(q) (not shown in FIG. 3A)is programmed to be equal to 1. All other selection inputs such as,Last-X^(n−1) 352, Last-X^(n−2) (not shown in FIG. 3A), . . . , Last-X⁰354, are programmed to have a value of zero.

The value of each selection input, such as Last-X^(n−1) 352,Last-X^(n−2) (not shown in FIG. 3A), . . . , Last-X⁰ 354 determineswhich input lines 362, 370, 394, 358, 392, . . . , 387, 386, 395, 358,is selected at the corresponding multiplexers, M_(b) ^(n−1) M_(c)^(n−1), . . . , M_(b) ⁰, M_(c) ⁰ to be output from the multiplexersM_(b) ^(n−1) M_(c) ^(n−1), . . . , M_(b) ⁰, M_(c) ⁰.

For example, if selection input Last-X^(n−1) 352 is programmed to havethe value of 1, multiplexer M_(b) ^(n−1) 326 and multiplexer M_(c)^(n−1) 328 will each receive the value 1 as an input. In FIG. 3A, it canbe seen that multiplexer M_(b) ^(n−1) 326 and multiplexer M_(c) ^(n−1)328 each has 2 input lines, labeled “1” and “0”. Since the value 1 isreceived as the selection input by multiplexer M_(b) ^(n−1) andmultiplexer M_(c) ^(n−1), multiplexer M_(b) ^(n−1) and multiplexer M_(c)^(n−1) will each select the input line labeled “1” to be their outputfor a particular cycle.

As explained herein, there is no Last-X^(n) selection input becausethere are no multiplexers that control the primary input into the XORgate, XOR^(n) 316. XOR^(n) 316, being the first XOR gate in an N-bitcapable CRC generator will always receive the primary input.

In FIG. 3A, multiplexer M_(out) 342 has N+1 input lines, namely, A^(n)344, A^(n−1) 346, . . . , up to A⁰ 348. If selection input Last-X^(n−1)352 has a value of 1, then multiplexer M_(out) 342 will select A^(n−1)346 to be CRC output 350. Similarly, if Last-X^(n−2) (not shown in FIG.3A) has a value of 1, then multiplexer M_(out) 342 will select A^(n−2)(not shown in FIG. 3A) to be CRC output 350, and so on.

Even though there is no Last-X^(n) selection input, the effect of aselection input Last-X^(n) can be obtained by making the selection ofA^(n) 344 as the default selection when all the selection inputs,namely, Last-X^((n−1)) 352, Last-X^((n−2)) (not shown in FIG. 3A),Last-X⁰ 354 have a value of zero.

Additionally, multiplexers with the subscript “b”, such as M_(b)^((n−1)) 326, M_(b) ^((n−2)) (not shown in FIG. 3A), M_(b) ^((n−3)) (notshown in FIG. 3A), . . . , M_(b) ⁰ 332 are communicatively coupled toeach other. Specifically, line 392 is an output line from M_(b) ^((n−1))326. Line 392 is also an input line to M_(b) ^((n−2)) (not shown in FIG.3A). As previously explained herein, line 393 is shown as an output linefrom multiplexer M_(b) ⁰ 332. Line 393 is also an input line to shiftregister X⁰ 314.

Multiplexers with the subscript “c” each receive a primary input, P 356.For example, multiplexers M_(c) ^((n−1)) 328, M_(c) ^((n−2)) (not shownin FIG. 3A), M_(c) ^((n−3)) (not shown in FIG. 3A), . . . , M_(c) ⁰ 334each receive a primary input, P 356. XOR gate XOR^(n) 316 also receivesprimary input, P 356. Typically, primary input P 356 is a bitstream thatis input into the XOR gates at the rate of one bit per cycle.

All multiplexers in the N-bit capable CRC generator have 2 input lines.One input line is labeled “1” and the other input line is labeled “0” asindicated in FIG. 3A.

The arrangement of the components in List B, i.e. the components thatnot shown in FIG. 3A, are the same as the arrangement of the componentsY^((n−1)) 338, XOR^((n−1)) 318, M_(a) ^((n−1)) 324, M_(b) ^((n−1)) 326,and M_(c) ^((n−1)) 328 relative to each other.

3.0 Illustrative Example of the Flexibility of an N-Bit Capable CRCGenerator

Typically, N is equal to 64 or larger for the universal CRC generator.However, for simplicity of explanation, assume that that N=3 for theN-bit capable CRC generator. FIG. 5 is a block diagram that illustratesa 3-bit capable CRC generator 500. A 3-bit capable CRC generator can beused for polynomial key words of orders ranging from 1 to 3.

In FIG. 5, shift register X³ 506 is communicatively coupled tocorresponding XOR gate, XOR³ 504. Specifically, line 550 is an outputline from shift register X³ 506. Line 550 is also an input line to XORgate, XOR³ 504.

Further, shift register X³ 506 is communicatively coupled to adjacentmultiplexers M_(a) ³ 502 and M_(a) ² 508. Specifically, line 548 is anoutput line from shift register X³ 506. Line 548 is also an input lineinto M_(a) ³ 502. Line 554 is output line from M_(a) ² 508. Line 554 isalso an input line into shift register X³ 506.

Similarly, shift register X² 516 is communicatively coupled tocorresponding XOR gate, XOR² 514, and to adjacent multiplexers M_(a) ²508 and M_(a) ¹ 518. Specifically, line 566 is an output line from shiftregister X² 516. Line 566 is also an input line to XOR gate, XOR² 514.Line 568 is an output line from shift register X² 516. Line 568 is alsoan input line into multiplexer M_(a) ² 508. Line 572 is output line frommultiplexer M_(a) ¹ 518. Line 572 is also an input line into shiftregister X² 516.

Shift register X¹ 526 is communicatively coupled to corresponding XORgate, XOR¹ 524, and to adjacent multiplexers M_(a) ¹ 518 and M_(a) ³528. Specifically, line 584 is an output line from shift register X¹526. Line 584 is also an input line to XOR gate, XOR¹ 524. Line 586 isan output line from shift register X¹ 526. Line 586 is also an inputline into multiplexer M_(a) ¹ 518. Line 590 is output line frommultiplexer M_(a) ⁰ 528. Line 590 is also an input line into shiftregister X¹ 526.

Shift register X⁰ 536 is communicatively coupled to XOR gate, XOR⁰ 534.In addition, shift register X⁰ 536 is communicatively coupled toadjacent multiplexer M_(a) ⁰ 528. Specifically, line 595 is an outputline from shift register X⁰ 536. Line 595 is also an input line to XORgate, XOR⁰ 534. Line 593 is an output line from shift register X⁰ 536.Line 593 is also an input line into multiplexer M_(a) ⁰ 528. Line 590 isoutput line from multiplexer M_(a) ⁰ 528.

Further, all shift registers X³ 506, X² 516, X¹ 526, X⁰ 536 arecommunicatively coupled to multiplexer M_(out) 589 via output lines A³546, A² 570, A¹ 588, and A⁰ 591, respectively. CRC Output 534 is theoutput of the 3-bit capable CRC generator 500.

Each XOR gate is additionally communicatively coupled to either one ortwo corresponding adjacent multiplexers. In FIG. 5, XOR gate, XOR³ 504is communicatively coupled to one adjacent corresponding multiplexerM_(a) ³ 502. Line 552 is an output line from XOR gate, XOR³ 504. Line552 is also an input line to multiplexer M_(a) ³ 502.

Similarly, XOR gate, XOR² 514, is communicatively coupled to adjacentcorresponding multiplexers M_(a) ² 508 and M_(c) ² 512. Line 564 is anoutput line from XOR gate, XOR² 514. Line 564 is also an input line tomultiplexer M_(a) ² 508. Line 562 is an output line from multiplexerM_(c) ² 512. Line 562 is also an input line to XOR gate, XOR² 514.

XOR gate, XOR¹ 524, is communicatively coupled to adjacent correspondingmultiplexers M_(a) ¹ 518 and M_(c) ¹ 522. Line 582 is an output linefrom XOR gate, XOR¹ 524. Line 582 is also an input line to multiplexerM_(a) ¹ 518. Line 580 is an output line from multiplexer M_(c) ¹ 522.Line 580 is also an input line to XOR gate, XOR¹ 524.

XOR gate, XOR⁰ 534, is communicatively coupled to adjacent correspondingmultiplexers M_(a) ⁰ 528 and M_(c) ¹ 532. Line 597 is an output linefrom XOR gate, XOR⁰ 534. Line 597 is also an input line to multiplexerM_(a) ⁰ 528. Line 598 is an output line from multiplexer M_(c) ⁰ 532.Line 598 is also an input line to XOR gate, XOR⁰ 534.

Programmable registers Y³ 538, Y² 540, Y¹ 542, and Y⁰ 544 are eachcommunicatively coupled to corresponding multiplexers M_(a) ³ 502, M_(a)² 508, M_(a) ¹ 518, M_(a) ⁰ 528 respectively.

For example, programmable register Y³ 502 is communicatively coupled toM_(a) ³ 502. Similarly, programmable register Y² 540 is coupled to M_(a)² 508. Programmable register Y¹ 532 is coupled to M_(a) ¹ 518.Programmable register Y⁰ 544 is coupled to M_(a) ⁰ 528.

For ease of explanation, multiplexers with the same superscript asillustrated in FIG. 5 are said to belong to the same family. As can beseen in FIG. 5, multiplexers that belong to the same family arecommunicatively coupled to form part of a feedback loop. For example,multiplexer M_(a) ² 508 is communicatively coupled to mulitplexer M_(b)² 510 that is in turn communicatively coupled to mulitplexer M_(c) ²512. Specifically, line 556 is an output line from multiplexer M_(a) ²508. Line 556 is also an input line to multiplexer M_(b) ² 510. Line 560is an input line from multiplexer M_(b) ² 510 to mulitplexer M_(c) ²512.

Similarly, M_(a) ¹ 518 is communicatively coupled to M_(b) ¹ 520 that isin turn communicatively coupled to M_(c) ¹ 522. Specifically, line 574is an output line from multiplexer M_(a) ¹ 518. Line 574 is also aninput line to multiplexer M_(b) ¹ 520. Line 578 is an input line frommultiplexer M_(b) ¹ 520 to mulitplexer M_(c) ¹ 522.

M_(a) ⁰ 528 is communicatively coupled to M_(b) ⁰ 530 that is in turncommunicatively coupled to M_(c) ⁰ 532. Specifically, line 592 is anoutput line from multiplexer M_(a) ⁰ 528. Line 592 is also an input lineto multiplexer M_(b) ⁰ 530. Line 596 is an input line from multiplexerM_(b) ⁰ 530 to mulitplexer M_(c) ⁰ 532.

However, M_(a) ³ 502, being the sole member in its family iscommunicatively coupled to multiplexer M_(b) ² 510. Line 547 is anoutput line from multiplexer M_(a) ³ 502 to multiplexer M_(b) ² 510.

Inputs Last-X² 583, Last-X¹ 587, and Last-X⁰ 585 are selection inputsinto corresponding multiplexers with subscripts “b” and “c” and whichbelong to the same family. For example, Last-X² 583 is a selection inputinto multiplexers M_(b) ² 510 and M_(c) ² 512. Last-X¹ 587 is aselection input into multiplexers M_(b) ¹ 520 and M_(c) ¹ 522. Last-X⁰585 is a selection input into multiplexers M_(b) ⁰ 530 and M_(c) ⁰ 532.Further, all selection inputs Last-X² 583, Last-X¹ 587, and Last-X⁰ 585are input into multiplexer M_(out) 589.

Additionally, multiplexers with the subscript “b”, such as M_(b) ² 510,M_(b) ¹ 520. M_(b) ⁰ 530 are communicatively coupled to each other.Multiplexers with the subscript “c” each receive a primary input, P 501through line 503. For example, multiplexers M_(c) ² 512, M_(c) ¹ 522and, M_(c) ⁰ 532 each receive a primary input, P 501. XOR gate XOR³ 504also receives primary input, P 501 through line 503. Typically, primaryinput P 501 is a bitstream that is to be checked for error by the CRCgenerator 500. Primary input P 501 is input into the XOR gates at therate of one bit per cycle.

As a first illustration, assume that a CRC generator is needed toimplement a given 320 polynomial key word of order 3. Further assumethat the given polynomial is as follows:X³+X²+1

The 3-bit capable CRC described with reference to FIG. 5 can beconverted to specifically implement the polynomial key word, X³+X²⁺¹. Inother words, by programming the values of the Y registers and the Last-Xselection inputs, the 3-bit capable CRC generator becomes a X³+X²+1 keyword CRC generator. For purposes of explanation, the given polynomialkey word is re-written to explicitly show coefficients and missingterms. Thus, the given polynomial key word, X³+X²+1, can be re-writtenas:(1)X³+(1)X²+(0)X¹+(1)X⁰

Referring to FIG. 5, programmable register Y³ 538 corresponds tocoefficient of X³ of the given key word polynomial. Thus, programmableregister Y³ 538 is programmed to have the value of 1. In response toreceiving the value of 1 from programmable register Y³ 538, multiplexerM_(a) ³ 502, will select input line labeled “1”.

Similarly, programmable register Y² 540 corresponds to coefficient X² ofthe given key word polynomial. Thus, programmable register Y² 540 isprogrammed to have the value of 1. In response to receiving the value of1 from programmable register Y² 540, multiplexer M_(a) ² 508, willselect input line labeled “1”.

Programmable register Y¹ 542 corresponds to coefficient X⁰ of the givenkey word polynomial. Thus, programmable register Y¹ 542 is programmed tohave the value of 0. In response to receiving the value of 0 fromprogrammable register Y¹ 542, multiplexer M_(a) ¹ 518, will select inputline labeled “0”.

Programmable register Y⁰ 544 corresponds to coefficient X⁰ of the givenkey word polynomial. Thus, programmable register Y⁰ 544 is programmed tohave the value of 1. In response to receiving the value of 1 fromprogrammable register Y⁰ 544, multiplexer M_(a) ⁰ 528, will select inputline labeled

The Last-X selection inputs are programmed to be a specific value basedon the most significant bit (MSB). FIG. 6 is a block diagram thatillustrates the position of the MSB that is associated with thepolynomial key word, X³+x²⁺¹. In FIG. 6, bit 610 has the value of the Y³register that is programmed to have a value of 1 described above. Sincethe first occurring “1” bit corresponds to the value of the Y³ register,bit 610 represents the MSB.

Similarly, bit 612 has the value of the Y² register that is programmedto have a value of 1. Bit 614 has the value of the Y¹ register that isprogrammed to have a value of 0. Bit 616 has the value of the Y⁰register that is programmed to have a value of 1. Bit 616 is the LSB.

Since the first occurring “1” bit corresponds to the value of the Y³register, all Last-X selection inputs, namely, Last-X² 583, Last-X¹ 587,and Last-X¹ 585 in FIG. 5 are programmed to have a value of zero.

The value of each Last-X selection input determines which input isselected at the corresponding multiplexers to be output from saidmultiplexers. For example, since selection input Last-X² 583 isprogrammed to have the value of 0, multiplexer M_(b) ² 510 andmultiplexer M_(c) ² 512 will each receive the value 0 as an input. InFIG. 5, it can be seen that multiplexer M_(b) ² 510 and multiplexerM_(c) ² 512 each has 2 input lines, labeled “1” and “0”. Since the value0 is received as the selection input, multiplexer M_(b) ² 510 andmultiplexer M_(c) ² 512 will each select the input line labeled “0” tobe their output for a particular cycle.

In FIG. 5, multiplexer M_(out) 589 has 4 input lines, namely, A³ 546, A²570, A¹ 588, A⁰ 591. Since all the selection inputs, namely, Last-X²583, Last-X¹ 587, Last-X⁰ 585, have the value of 0, multiplexer M_(out)589 will select A³ 546 to be CRC output 534.

Thus, by programming the Y registers and the Last-X selection inputs asdescribed above, the 3-bit capable CRC generator is equivalent to theCRC generator as described in FIG. 1 herein.

Further, the same 3-bit capable CRC generator can be programmed toimplement a given polynomial key word that is of an order that is lowerthan 3. Assume that the given polynomial is as follows:X¹+1

For purposes of explanation, the given polynomial key word, X¹+1, isre-written to explicitly show coefficients and missing terms. Thus, thegiven polynomial key word, X¹+1, can be re-written as:(0)X³+(0)X¹+(1)X¹+(1)X⁰

In FIG. 5 programmable register Y³ 538 corresponds to coefficient of X³of the given key word polynomial. Thus, programmable register Y³ 538 isprogrammed to have the value of 0. In response to receiving the value of0 from programmable register Y³ 538, multiplexer M_(a) ³ 502, willselect input line labeled “0”.

Similarly, programmable register Y² 540 corresponds to coefficient X² ofthe given key word polynomial. Thus, programmable register Y² 540 isprogrammed to have the value of 0. In response to receiving the value of0 from programmable register Y² 540, multiplexer M_(a) ² 508, willselect input line labeled “0”.

Programmable register Y¹ 542 corresponds to coefficient X¹ of the givenkey word polynomial. Thus, programmable register Y¹ 542 is programmed tohave the value of 1. In response to receiving the value of 1 fromprogrammable register Y¹ 542, multiplexer M_(a) ¹ 518, will select inputline labeled “1”.

Programmable register Y⁰ 544 corresponds to coefficient X⁰ of the givenkey word polynomial. Thus, programmable register Y⁰ 544 is programmed tohave the value of 1. In response to receiving the value of 1 fromprogrammable register Y⁰ 544, multiplexer M_(a) ⁰ 528, will select inputline labeled “1”.

The Last-X selection inputs are programmed to be a specific value basedon the most significant bit (MSB) of the Y registers. FIG. 7 is a blockdiagram that illustrates the position of the MSB that is associated witha X¹+X⁰ key word. In FIG. 7, bit 710 has the value of the register Y³that is programmed to have a value of 0 described above. Similarly, bit712 has the value of the Y² register that is programmed to have a valueof 0.

Bit 714 has the value of the Y¹ register that is programmed to have avalue of 1. Since the first occurring “1” bit corresponds to the valueof the Y¹ register, bit 714 represents the MSB. Bit 716 has the value ofthe Y⁰ register that is programmed to have a value of 1. Bit 716 is theLSB.

Since the first occurring “1” bit corresponds to the value of registerY¹, selection input Last-X¹ 587 is programmed to have a value of 1, andselection inputs Last-X² 583 and Last-X⁰ 585 are programmed to have avalue of 0.

The value of each Last-X selection input determines which input isselected at the corresponding multiplexers to be output from saidmultiplexers.

Referring back to FIG. 5, since selection input Last-X² 583 has thevalue 0, multiplexer M_(b) ² 510 and multiplexer M_(c) ² 512 will eachselect the input line labeled “0” to be their output for a particularcycle. Similarly, since selection input Last-X⁰ 585 has the value 0,multiplexer M_(b) ⁰ 530 and multiplexer M_(c) ⁰ 532 will each select theinput line labeled “0” to be their output for a particular cycle.

In contrast, since selection input Last-X¹ 587 has the value 1,multiplexer M_(b) ¹ 520 and multiplexer M_(c) ¹ 522 will each select theinput line labeled “1” to be their output for a particular X⁰ cycle.

In FIG. 5, multiplexer M_(out) 589 has 4 input lines, namely, A³ 546, A²570, A¹ 588, A⁰ 591. Since the selection input Last-X¹ 587 has the valueof 1, multiplexer M_(out) 589 will select A¹ 588 to be CRC output 534.

Thus, by programming the Y registers and the Last-X selection inputs asdescribed above, the 3-bit capable CRC generator 500 is equivalent tothe CRC generator as described in FIG. 2.

5.0 Extensions and Alternatives

In the foregoing specification, the invention has been described withreference to specific embodiments thereof. It will, however, be evidentthat various modifications and changes may be made thereto withoutdeparting from the broader spirit and scope of the invention. Thespecification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense.

1. A Cyclic Redundancy Check (CRC) system, comprising: N+1 shiftregisters; N+1 logic gates having first inputs that communicate withoutputs of corresponding ones of said N+1 shift registers; N+1programmable registers, wherein each of said N+1 programmable registersstores a corresponding CRC coefficient of a 3^(rd) to Nth order CRCpolynomial key word, wherein N is an integer greater than two; and N+1multiplexers that communicate with outputs of corresponding ones of saidN+1 logic gates, wherein at least N of said N+1 multiplexers communicatewith corresponding ones of at least N of said N+1 programmableregisters.
 2. The CRC system of claim 1 further comprising Mmultiplexers that communicate with inputs of at least N of said N+1logic gates, where M=N.
 3. The CRC system of claim 2 further comprisingP multiplexers that communicate with corresponding outputs of at least Nof said N+1 multiplexers and with corresponding inputs of said Mmultiplexers.
 4. The CRC system of claim 1 further comprising an outputmultiplexer that communicates with outputs of said N+1 shift registers.5. A Cyclic Redundancy Check (CRC) system, comprising: N+1 shiftregister means for shifting; N+1 logic means for providing a logicfunction and having first inputs that communicate with outputs ofcorresponding ones of said N+1 shift register means; N+1 programmablestoring means for storing, wherein each of said N+1 programmable storingmeans stores a corresponding CRC coefficient of a 3^(rd) to Nth orderCRC polynomial key word, wherein N is an integer greater than two; andN+1 multiplexing means for multiplexing that communicate with outputs ofcorresponding ones of said N+1 logic means, wherein at least N of saidN+1 multiplexing means communicate with corresponding ones of at least Nof said N+1 programmable storing means.
 6. The CRC system of claim 5further comprising M multiplexing means that communicate with inputs ofat least N of said N+1 logic means, where M=N.
 7. The CRC system ofclaim 6 further comprising P multiplexing means that communicate withcorresponding outputs of at least N of said N+1 multiplexing means andwith corresponding inputs of said M multiplexing means.
 8. The CRCsystem of claim 5 further comprising output multiplexing means thatcommunicates with outputs of said N+1 shift register means.